Ultra-Fast Automatic Placement for FPGAs

Ultra-Fast Automatic Placement for FPGAs The demand for high-speed Field-Programmable Gate Array (FPGA) compilation tools has escalated for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing of circuits has grown more dramatically than the available computer power. Second, there exists a subset of users who are willing to accept a reduction in the quality of result (using a larger FPGA or more resources on a given FPGA) in exchange for a high-speed compilation. Third, high-speed compile has been a long-standing desire of users of FPGA-based custom computing machines, since their compile time requirements are ideally closer to those of regular computers. This thesis focuses on the placement phase of the compile process, and presents an ultra-fast placement algorithm for FPGAs. The algorithm is based on a combination of multiple-level, bottom-up clustering and hierarchical simulated annealing. It provides superior area results over a known high-quality placement tool on a set of large benchmark circuits, when both are restricted to a short run time. For example, in 10 seconds of placement time on a 300 MHz Sun UltraSPARC, the ultra-fast tool realizes an average wirelength improvement of 30% compared to the high-quality tool. It can also generate a placement for a 100,000-gate circuit in 10 seconds that is only 31% worse than a high-quality placement that takes 524 seconds using a pure simulated annealing implementation. For this circuit, the ultra-fast tool achieves this level of placement quality 5 times faster than the high-quality tool. In addition, when operating in its fastest mode, the ultra-fast placement tool can provide an accurate estimate of the wirelength achievable with good quality placement (within 6%, on average). This can be used, in conjunction with a routing predictor, to very quickly determine the routability of a given circuit on a given FPGA device. iii Acknowledgments